Jack Shkifati

09 / 10 · Systems · Computer architecture

E20 Assembler, CPU Simulator & Cache

A two-pass E20 assembler, an object-oriented instruction-set simulator for the full ISA, and a configurable two-level cache simulator, all in C++ and validated against 40+ test scenarios.

Play the demo
40+
test scenarios
L1/L2
cache with LRU
E20 Assembler, CPU Simulator & Cache: project image from Jack’s site
Fig. 00 · From the project
Fig. 01

Try it

AI-generated voice and avatar
Interactive demoStep a tiny E20 CPU through real assembly
01

Problem & approach

The problem

Run E20 programs end to end: turn assembly source into machine code, execute it instruction by instruction, and model the cache between processor and memory.

The approach

Three pieces in C++: a two-pass assembler, an instruction-set simulator, and an L1/L2 cache simulator with an LRU eviction policy.

02

How it works

  1. AssembleA two-pass assembler: regex parsing, label resolution and bit-field machine-code encoding.
  2. SimulateAn object-oriented simulator implements the full ISA with sign extension and 16-bit register and memory masking.
  3. ValidateValidated against 40+ test scenarios.
  4. CacheA configurable two-level (L1/L2) cache: direct-mapped, n-way set-associative or fully associative, with LRU eviction and per-access hit/miss logs.
03

Results & stack

40+
test scenarios
L1/L2
cache with LRU
  • C++
  • Assembly
  • Computer architecture